Mixed-language designs with Xilinx tools: be careful

I had a couple of bugs that each took me a few days to track down, because it just didn’t occur to me that the compiler might just be wrong. Googling around for related issues didn’t help me, but perhaps this will save someone else some time.

Using the version of Xst package with ISE 10.x, Verilog modules instantiated in VHDL files can get incorrectly optimized away. Moving to 12.x solved that issue. It wouldn’t have even occurred to me to look for that had a co-worker not mentioned that he had problems with some of his code getting optimized away in 9.X, when he was creating a multi-banked RAM (without mixed-language code) – the synthesis tool decided that one bank just wasn’t necessary, and removed it entirely. Moving backwards to version 8.x fixed his issue.

Even in the latest version, there are still mixed language issues. A VHDL IOBUF connected to a Verilog module may get Xs on the output of the IOBUF in ISim even if T, the IOBUF select, is high, and the output of the IOBUF is only connected to Verilog module inputs. Switching to a Verilog wrapper and instantiating the IOBUF in Verilog fixed that problem.  I never would have thought to try swapping out a VHDL instantiation for an identical Verilog instantiation had I not run into a mixed language previously.

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Mixed-language designs with Xilinx tools: be careful

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